One of test items for various devices such as for high-speed communication and high-speed serial interface is a jitter tolerance test. In this test, confirmation is made as to whether or not a device normally operates when jitter is added to clock signals or data, which are inputted to the device.
A semiconductor testing apparatus is an apparatus for conducting various tests for devices. In case the jitter tolerance test is conducted using the semiconductor testing apparatus, jitter is required to be added to timing edges produced by a timing generator. Known jitter generators for adding jitter to clock signals or the like include one having a configuration in which a variable delay circuit is provided for delaying clock signals or the like (refer to Patent Document 1, for example). In this jitter generator, sinusoidal offset voltage and output voltage of a ramp generator are compared with each other to impart sinusoidal fluctuation to the timing of alteration of the clock signals.
Patent Document 1: Japanese Patent Laid-Open No. 6-104708 (pp. 3 and 4, and FIGS. 1 to 3)